To ensure the reliability of computer systems, errors in the data that is stored in electronic memory structures may be detected and corrected. Errors in memory have long been detected through the use of parity bits. Parity bits are bits that may be added to a memory structure to ensure the integrity of data stored in the memory. Each time that data is written to a memory, a logic circuit (e.g., a parity generation circuit) examines the data and determines the number of high data states (e.g., “1's”). The parity of the data stored in the memory is computed based upon the number of high data states. In the case of even parity bits, the logic circuit will calculate a parity bit value equal to “1” when the number of high data states in the memory is even and a parity bit value equal to “0” when the number of high data states in a memory is odd. It is also possible to have odd parity bits, wherein the logic circuit will calculate a parity bit value equal to “1” when the number of high data states in the memory is odd and a parity bit value equal to “0” when the number of high data states in a memory is even. When data is read back from the memory, the logic circuit reads back the bits and again determines a parity bit value (e.g., if there are an odd or an even number of ones). Comparison of the parity bit values can detect an error in the memory.
For example, FIG. 1 shows a block diagram of a memory 102 configured to store a data byte comprising eight data bits 104a-104g and a parity bit 106 at a first time T1, when data is written into the memory, and at a later time T2, when data is read from the memory. At time the memory 102 stores a data byte having an odd number of bits having a data value of “1” (e.g., 104b, 104e, 104f), resulting in an even parity bit 106 having a value of “1”. Between time T1 and time T2 an event occurs that causes a value of the data bit stored in memory element 104d to change its value from “0” to “1”. Therefore, at the later time T2, the memory 102′ stores a data byte having an even number of bits having a data value of “1” (e.g., 104b, 104d, 104e, 104f), resulting in an even parity bit 106 having a value of “0”. Because the value of the parity bit 106 at time T1 is different than the value of the parity bit 106 at time T2, an error is present in the memory.
While parity bits may easily detect single bit errors, the use of parity bits to correct data (e.g., as done in Hamming-Code schemes) requires a large increase in hardware and energy consumption of an integrated circuit and therefore is not desirable. Alternatively, data may be detected and corrected by the implementation of majority decision-makers or voters. However, such methods also use large chip areas and consume large amounts of power.